How microchips are made

To understand what the main difference between these two technologies is, it is necessary to make a brief digression into the technology itself for the production of modern processors or integrated circuits.

As is known from the school physics course, in modern electronics the main components of integrated circuits are p-type and n-type semiconductors (depending on the type of conductivity). A semiconductor is a substance that is superior in conductivity to dielectrics, but inferior to metals. Both types of semiconductors can be based on silicon (Si), which in its pure form (the so-called intrinsic semiconductor) is a poor conductor of electric current, but the addition (incorporation) of a certain impurity into silicon makes it possible to radically change its conductive properties. There are two types of impurities: donor and acceptor. The donor impurity leads to the formation of n-type semiconductors with an electronic type of conductivity, while the acceptor impurity leads to the formation of p-type semiconductors with a hole type of conductivity. Contacts of p- and n-semiconductors make it possible to form transistors - the main structural elements of modern microcircuits. Such transistors, called CMOS transistors, can be in two basic states: open, when they conduct electricity, and closed, while they do not conduct electricity. Since CMOS transistors are the main elements of modern microcircuits, let's talk about them in more detail.

How a CMOS transistor works

The simplest n-type CMOS transistor has three electrodes: source, gate and drain. The transistor itself is made in a p-type semiconductor with hole conductivity, and n-type semiconductors with electronic conductivity are formed in the drain and source regions. Naturally, due to the diffusion of holes from the p-region to the n-region and the reverse diffusion of electrons from the n-region to the p-region, depleted layers (layers in which there are no main charge carriers) are formed at the transition boundaries of the p- and n-regions. In the normal state, that is, when no voltage is applied to the gate, the transistor is in a "locked" state, that is, it is not able to conduct current from the source to the drain. The situation does not change even if a voltage is applied between the drain and the source (we do not take into account the leakage currents caused by the movement of minority charge carriers under the influence of the generated electric fields, that is, holes for the n-region and electrons for the p-region).

However, if a positive potential is applied to the gate (Fig. 1), then the situation will change radically. Under the influence of the electric field of the gate, holes are pushed deep into the p-semiconductor, and electrons, on the contrary, are drawn into the region under the gate, forming an electron-rich channel between the source and drain. If a positive voltage is applied to the gate, these electrons begin to move from the source to the drain. In this case, the transistor conducts current - they say that the transistor "opens". If the voltage is removed from the gate, the electrons cease to be drawn into the region between the source and drain, the conductive channel is destroyed and the transistor ceases to pass current, that is, it “locks”. Thus, by changing the voltage at the gate, you can turn on or off the transistor, in the same way as you can turn on or off a conventional toggle switch, controlling the flow of current through the circuit. This is why transistors are sometimes called electronic switches. However, unlike conventional mechanical switches, CMOS transistors have virtually no inertia and are capable of switching from on to off state trillions of times per second! It is this characteristic, that is, the ability to instantly switch, that ultimately determines the speed of the processor, which consists of tens of millions of such simple transistors.

So, a modern integrated circuit consists of tens of millions of the simplest CMOS transistors. Let us dwell in more detail on the manufacturing process of microcircuits, the first stage of which is the preparation of silicon substrates.

Step 1. Growing blanks

The creation of such substrates begins with the growth of a cylindrical silicon single crystal. Subsequently, round plates (wafers) are cut from such single-crystal blanks (blanks), the thickness of which is approximately 1/40 inch, and the diameter is 200 mm (8 inches) or 300 mm (12 inches). This is the silicon substrates used for the production of microcircuits.

When forming wafers from silicon single crystals, the fact is taken into account that for ideal crystal structures, the physical properties largely depend on the chosen direction (anisotropy property). For example, the resistance of a silicon substrate will be different in the longitudinal and transverse directions. Similarly, depending on the orientation of the crystal lattice, the silicon crystal will react differently to any external influences associated with its further processing (for example, etching, sputtering, etc.). Therefore, the plate must be cut from a single crystal in such a way that the orientation of the crystal lattice relative to the surface is strictly maintained in a certain direction.

As already noted, the diameter of a silicon single crystal blank is either 200 or 300 mm. Moreover, a diameter of 300 mm is a relatively new technology, which we will discuss below. It is clear that a plate of such a diameter can accommodate far more than one chip, even if we are talking about an Intel Pentium 4 processor. Indeed, several dozen microcircuits (processors) are formed on one such substrate plate, but for simplicity, we will consider only a small area of ​​one future microprocessor.

Step 2. Application of a protective film of dielectric (SiO2)

After the formation of the silicon substrate, the stage of creating the most complex semiconductor structure begins.

To do this, it is necessary to introduce the so-called donor and acceptor impurities into silicon. However, the question arises - how to implement the introduction of impurities according to a precisely given pattern-pattern? To make this possible, those areas where impurities are not required are protected with a special silicon dioxide film, leaving only those areas that are exposed to further processing (Fig. 2). The process of forming such a protective film of the desired pattern consists of several stages.

At the first stage, the entire silicon wafer is completely covered with a thin film of silicon dioxide (SiO2), which is a very good insulator and acts as a protective film during further processing of the silicon crystal. The wafers are placed in a chamber where, at high temperature (from 900 to 1100 °C) and pressure, oxygen diffuses into the surface layers of the wafer, leading to the oxidation of silicon and the formation of a surface film of silicon dioxide. In order for the silicon dioxide film to have a precisely specified thickness and not contain defects, it is necessary to strictly maintain a constant temperature at all points of the plate during the oxidation process. If not the entire wafer is to be covered with a silicon dioxide film, then a Si3N4 mask is preliminarily applied to the silicon substrate to prevent unwanted oxidation.

Step 3 Apply Photoresist

After the silicon substrate is covered with a protective film of silicon dioxide, it is necessary to remove this film from those places that will be subjected to further processing. The film is removed by etching, and to protect the remaining areas from etching, a layer of the so-called photoresist is applied to the surface of the plate. The term "photoresist" refers to light-sensitive and resistant to aggressive factors compositions. The compositions used must, on the one hand, have certain photographic properties (become soluble under the influence of ultraviolet light and be washed out during the etching process), and on the other hand, resistive, allowing them to withstand etching in acids and alkalis, heating, etc. The main purpose of photoresists is to create a protective relief of the desired configuration.

The process of applying a photoresist and its further irradiation with ultraviolet light according to a given pattern is called photolithography and includes the following main operations: formation of a photoresist layer (substrate treatment, deposition, drying), formation of a protective relief (exposure, development, drying) and image transfer to the substrate (etching, deposition etc.).

Before applying the photoresist layer (Fig. 3) to the substrate, the latter is subjected to pretreatment, as a result of which its adhesion to the photoresist layer is improved. To apply a uniform layer of photoresist, the centrifugation method is used. The substrate is placed on a rotating disk (centrifuge), and under the influence of centrifugal forces, the photoresist is distributed over the surface of the substrate in an almost uniform layer. (Speaking of a practically uniform layer, one takes into account the fact that under the action of centrifugal forces the thickness of the formed film increases from the center to the edges, however, this method of applying the photoresist allows one to withstand fluctuations in the layer thickness within ± 10%.)

Step 4. Lithography

After the application and drying of the photoresist layer, the stage of formation of the necessary protective relief begins. The relief is formed as a result of the fact that under the action of ultraviolet radiation falling on certain areas of the photoresist layer, the latter changes the properties of solubility, for example, the illuminated areas cease to dissolve in the solvent, which remove areas of the layer that have not been exposed to illumination, or vice versa - the illuminated areas dissolve. According to the way the relief is formed, photoresists are divided into negative and positive. Negative photoresists under the action of ultraviolet radiation form protective areas of the relief. Positive photoresists, on the contrary, under the influence of ultraviolet radiation acquire the properties of fluidity and are washed out by the solvent. Accordingly, a protective layer is formed in those areas that are not exposed to ultraviolet radiation.

To illuminate the desired areas of the photoresist layer, a special mask template is used. Most often, optical glass plates with opaque elements obtained by a photographic or other method are used for this purpose. In fact, such a template contains a drawing of one of the layers of the future microcircuit (there may be several hundred such layers in total). Because this pattern is a reference, it must be made with great precision. In addition, taking into account the fact that a lot of photoplates will be made using one photomask, it must be durable and resistant to damage. From this it is clear that a photomask is a very expensive thing: depending on the complexity of the microcircuit, it can cost tens of thousands of dollars.

Ultraviolet radiation passing through such a pattern (Fig. 4) illuminates only the desired areas of the surface of the photoresist layer. After irradiation, the photoresist is subjected to development, as a result of which unnecessary parts of the layer are removed. This opens the corresponding part of the layer of silicon dioxide.

Despite the apparent simplicity of the photolithographic process, it is this stage of microchip production that is the most difficult. The fact is that, in accordance with Moore's prediction, the number of transistors on a single chip is growing exponentially (doubling every two years). Such an increase in the number of transistors is possible only due to a decrease in their size, but it is precisely the decrease that “rests” on the lithography process. In order to make transistors smaller, it is necessary to reduce the geometric dimensions of the lines applied to the photoresist layer. But there is a limit to everything - it is not so easy to focus a laser beam to a point. The fact is that, in accordance with the laws of wave optics, the minimum spot size into which the laser beam is focused (in fact, this is not just a spot, but a diffraction pattern) is determined, among other factors, by the wavelength of the light. The development of lithographic technology since its invention in the early 70s has been in the direction of shortening the wavelength of light. This is what made it possible to reduce the size of the integrated circuit elements. Since the mid-1980s, ultraviolet radiation produced by a laser has been used in photolithography. The idea is simple: the wavelength of ultraviolet radiation is shorter than the wavelength of visible light, therefore it is possible to get finer lines on the surface of the photoresist. Until recently, deep ultraviolet radiation (Deep Ultra Violet, DUV) with a wavelength of 248 nm was used for lithography. However, when photolithography crossed the border of 200 nm, serious problems arose, for the first time calling into question the possibility of further use of this technology. For example, at a wavelength less than 200 µm, too much light is absorbed by the photosensitive layer, so the process of transferring the circuit template to the processor becomes more complicated and slower. Problems like these are driving researchers and manufacturers to look for alternatives to traditional lithographic technology.

The new lithography technology, called EUV lithography (Extreme UltraViolet - super-hard ultraviolet radiation), is based on the use of ultraviolet radiation with a wavelength of 13 nm.

The transition from DUV to EUV lithography provides more than a 10-fold reduction in wavelength and a transition to a range where it is comparable to the size of only a few tens of atoms.

The current lithographic technology allows to apply a pattern with a minimum conductor width of 100 nm, while EUV lithography makes it possible to print lines of much smaller width - up to 30 nm. Controlling ultrashort radiation is not as easy as it seems. Since EUV radiation is well absorbed by glass, the new technology involves the use of a series of four special convex mirrors that reduce and focus the image obtained after applying the mask (Fig. 5 , , ). Each such mirror contains 80 individual metal layers about 12 atoms thick.

Step 5 Etching

After the photoresist layer is illuminated, the etching stage begins to remove the silicon dioxide film (Fig. 8).

The pickling process is often associated with acid baths. This method of etching in acid is well known to radio amateurs who made printed circuit boards on their own. To do this, a pattern of tracks of the future board is applied to the foil textolite with a varnish that acts as a protective layer, and then the plate is lowered into a bath with nitric acid. Unnecessary sections of the foil are etched away, exposing a clean textolite. This method has a number of disadvantages, the main of which is the inability to accurately control the layer removal process, since too many factors affect the etching process: acid concentration, temperature, convection, etc. In addition, the acid interacts with the material in all directions and gradually penetrates under the edge of the photoresist mask, that is, it destroys the layers covered by the photoresist from the side. Therefore, in the production of processors, a dry etching method, also called plasma, is used. This method makes it possible to accurately control the etching process, and the destruction of the etched layer occurs strictly in the vertical direction.

Dry etching uses an ionized gas (plasma) to remove silicon dioxide from the wafer surface, which reacts with the silicon dioxide surface to form volatile by-products.

After the etching procedure, that is, when the desired areas of pure silicon are exposed, the rest of the photolayer is removed. Thus, a silicon dioxide pattern remains on the silicon substrate.

Step 6. Diffusion (ion implantation)

Recall that the previous process of forming the necessary pattern on a silicon substrate was required in order to create semiconductor structures in the right places by introducing a donor or acceptor impurity. The process of incorporation of impurities is carried out by means of diffusion (Fig. 9), i.e. uniform incorporation of impurity atoms into the crystal lattice of silicon. To obtain an n-type semiconductor, antimony, arsenic or phosphorus are usually used. To obtain a p-type semiconductor, boron, gallium or aluminum is used as an impurity.

Ion implantation is used for the dopant diffusion process. The process of implantation consists in the fact that the ions of the required impurity are “shot out” from the high-voltage accelerator and, having sufficient energy, penetrate into the surface layers of silicon.

So, at the end of the ion implantation stage, the necessary layer of the semiconductor structure has been created. However, in microprocessors there may be several such layers. An additional thin layer of silicon dioxide is grown to create the next layer in the resulting circuit diagram. After that, a layer of polycrystalline silicon and another layer of photoresist are applied. Ultraviolet radiation is passed through the second mask and highlights the corresponding pattern on the photo layer. Then the stages of photolayer dissolution, etching and ion implantation follow again.

Step 7 Sputtering and Deposition

The imposition of new layers is carried out several times, while “windows” are left for interlayer connections in the layers, which are filled with metal atoms; as a result, metal strips are created on the crystal - conducting regions. Thus, in modern processors, links are established between layers that form a complex three-dimensional scheme. The process of growing and processing all layers lasts several weeks, and the production cycle itself consists of more than 300 stages. As a result, hundreds of identical processors are formed on a silicon wafer.

In order to withstand the impacts that the wafers are subjected to during the layering process, silicon substrates are initially made thick enough. Therefore, before cutting the plate into individual processors, its thickness is reduced by 33% and dirt is removed from the reverse side. Then, a layer of a special material is applied to the back side of the substrate, which improves the fastening of the crystal to the case of the future processor.

Step 8. Final step

At the end of the formation cycle, all processors are thoroughly tested. Then, specific crystals that have already passed the test are cut out from the substrate plate using a special device (Fig. 10).

Each microprocessor is built into a protective housing, which also provides electrical connection of the microprocessor chip with external devices. The package type depends on the type and intended application of the microprocessor.

After being sealed into the housing, each microprocessor is retested. Faulty processors are rejected, and serviceable ones are subjected to stress tests. The processors are then sorted based on their behavior at various clock speeds and supply voltages.

Promising technologies

The technological process for the production of microcircuits (in particular, processors) has been considered by us in a very simplified way. But even such a superficial presentation makes it possible to understand the technological difficulties that one has to face when reducing the size of transistors.

However, before considering new promising technologies, let's answer the question posed at the very beginning of the article: what is the design norm of the technological process and how, in fact, does the design norm of 130 nm differ from the norm of 180 nm? 130 nm or 180 nm is a characteristic minimum distance between two adjacent elements in one layer of the microcircuit, that is, a kind of grid step to which the microcircuit elements are bound. At the same time, it is quite obvious that the smaller this characteristic size, the more transistors can be placed on the same chip area.

Currently, Intel processors use a 0.13 micron manufacturing process. This technology is used to manufacture the Intel Pentium 4 processor with the Northwood core, the Intel Pentium III processor with the Tualatin core, and the Intel Celeron processor. In the case of using such a technological process, the useful width of the transistor channel is 60 nm, and the thickness of the gate oxide layer does not exceed 1.5 nm. All in all, the Intel Pentium 4 processor contains 55 million transistors.

Along with increasing the density of transistors in a processor chip, the 0.13-micron technology, which replaced the 0.18-micron, has other innovations. First, it uses copper connections between the individual transistors (in 0.18 micron technology, the connections were aluminum). Secondly, 0.13 micron technology provides lower power consumption. For mobile technology, for example, this means that the power consumption of microprocessors becomes less, and the battery life is longer.

Well, the last innovation that was embodied in the transition to a 0.13-micron technological process is the use of silicon wafers (wafer) with a diameter of 300 mm. Recall that before that, most processors and microcircuits were manufactured on the basis of 200 mm wafers.

Increasing the wafer diameter reduces the cost of each processor and increases the yield of products of adequate quality. Indeed, the area of ​​a wafer with a diameter of 300 mm is 2.25 times larger than the area of ​​a wafer with a diameter of 200 mm, respectively, and the number of processors obtained from one wafer with a diameter of 300 mm is more than twice as large.

In 2003, the introduction of a new technological process with an even lower design standard, namely 90-nanometer, is expected. The new process technology that Intel will manufacture most of its products, including processors, chipsets and communications equipment, was developed at Intel's 300mm wafer pilot plant D1C in Hillsboro, Oregon.

On October 23, 2002, Intel Corporation announced the opening of a new $2 billion facility in Rio Rancho, New Mexico. The new plant, called F11X, will use state-of-the-art technology to manufacture processors on 300mm wafers using a 0.13 micron design process. In 2003, the plant will be transferred to a technological process with a design standard of 90 nm.

In addition, Intel has already announced the resumption of construction of another manufacturing facility at Fab 24 in Leixlip, Ireland, which is designed to fabricate semiconductor components on 300mm silicon wafers with a 90nm design rule. The new enterprise with a total area of ​​more than 1 million square meters. feet with especially clean rooms with an area of ​​160 thousand square meters. feet is expected to be operational in the first half of 2004 and will employ more than a thousand people. The cost of the object is about 2 billion dollars.

The 90nm process uses a number of advanced technologies. These include the world's smallest mass-produced CMOS transistors with a gate length of 50 nm (Figure 11), which increases performance while reducing power consumption, and the thinnest gate oxide layer of any transistor ever manufactured - only 1.2 nm (Figure 12), or less than 5 atomic layers, and the industry's first implementation of high performance stressed silicon technology.

Of the listed characteristics, perhaps only the concept of “stressed silicon” needs to be commented on (Fig. 13). In such silicon, the distance between atoms is greater than in a conventional semiconductor. This, in turn, allows the current to flow more freely, similar to how vehicles with wider lanes move more freely and faster.

As a result of all innovations, the performance of transistors is improved by 10-20%, while increasing production costs by only 2%.

In addition, the 90nm process uses seven layers per chip (Figure 14), one more layer than the 130nm process, and copper connections.

All of these features combined with 300mm silicon wafers provide Intel with performance, volume and cost advantages. Consumers benefit as well, as Intel's new process technology allows the industry to continue to evolve in accordance with Moore's Law, improving processor performance again and again.

Introduction. 2

1. Technologies for the production of microprocessors. 4

1.2 The main stages of production. eight

1.3 Growing silicon dioxide and creating conductive regions. nine

1.4 Testing. eleven

1.5 Manufacture of the case. eleven

1.6 Prospects for production. 12

2. Features of the production of microprocessors. eighteen

3. Technological stages of production of microprocessors. 26

3.1 How chips are made.. 26

1.2 It all starts with substrates. 27

1.3 Production of substrates. 27

1.4 Doping, diffusion. 29

1.5 Creating a mask. thirty

1.6 Photolithography. 31

Conclusion. 37

References.. 38

Introduction

Modern microprocessors are the fastest and smartest microcircuits in the world. They can perform up to 4 billion operations per second and are produced using many different technologies. Since the beginning of the 90s of the 20th century, when processors went into mass use, they have gone through several stages of development. The apogee of the development of microprocessor structures using existing technologies of 6th generation microprocessors was 2002, when it became available to use all the basic properties of silicon to obtain high frequencies with the least losses in production and creation of logic circuits. Now the efficiency of new processors is falling somewhat, despite the constant increase in the frequency of the crystals.

A microprocessor is an integrated circuit formed on a small silicon chip. Silicon is used in microcircuits due to the fact that it has semiconductor properties: its electrical conductivity is greater than that of dielectrics, but less than that of metals. Silicon can be made both an insulator that prevents the movement of electric charges, and a conductor - then electric charges will freely pass through it. The conductivity of a semiconductor can be controlled by introducing impurities.

The microprocessor contains millions of transistors connected to each other by the thinnest conductors made of aluminum or copper and used for data processing. This is how the inner tires are formed. As a result, the microprocessor performs many functions - from mathematical and logical operations to controlling the operation of other microcircuits and the entire computer.

One of the main parameters of the microprocessor is the frequency of the crystal, which determines the number of operations per unit of time, the frequency of the system bus, the amount of internal SRAM cache. The processor is marked by the frequency of the crystal. The frequency of the crystal is determined by the frequency of switching transistors from closed to open. The ability of a transistor to switch faster is determined by the manufacturing technology of the silicon wafers from which the chips are made. The dimension of the technological process determines the dimensions of the transistor (its thickness and gate length). For example, using the 90nm process that was introduced in early 2004, the transistor size is 90nm and the gate length is 50nm.

All modern processors use field-effect transistors. The transition to a new process technology allows you to create transistors with a higher switching frequency, lower leakage currents, and smaller sizes. Reducing the size allows you to simultaneously reduce the area of ​​​​the chip, and hence the heat dissipation, and a thinner gate allows you to apply less voltage for switching, which also reduces power consumption and heat dissipation.

1. Technologies for the production of microprocessors

Now there is an interesting trend in the market: on the one hand, manufacturing companies are trying to introduce new technical processes and technologies into their new products as soon as possible, on the other hand, there is an artificial restraint in the growth of processor frequencies. Firstly, marketers feel that the market is not fully prepared for the next change in processor families, and companies have not yet received enough profit from sales of currently produced CPUs - the stock has not dried up yet. The predominance of the importance of the price of the finished product over all other interests of companies is quite noticeable. Secondly, a significant reduction in the pace of the "frequency race" is due to the understanding of the need to introduce new technologies that really increase productivity with a minimum amount of technological costs. As already noted, manufacturers have encountered problems in the transition to new technical processes.

The technological norm of 90 nm turned out to be a rather serious technological barrier for many chip manufacturers. This is also confirmed by TSMC, which manufactures chips for many market giants such as AMD, nVidia, ATI, VIA. For a long time, she was unable to establish the production of chips using 0.09 micron technology, which led to a low yield of suitable crystals. This is one of the reasons why AMD has been postponing the release of its processors with SOI (Silicon-on-Insulator) technology for a long time. This is due to the fact that it is on this dimension of the elements that all sorts of previously not so noticeable negative factors such as leakage currents, a large spread of parameters and an exponential increase in heat release began to strongly manifest themselves. Let's figure it out in order.

As you know, there are two leakage currents: gate leakage current and subthreshold leakage. The first is caused by the spontaneous movement of electrons between the silicon substrate of the channel and the polysilicon gate. The second is the spontaneous movement of electrons from the source of the transistor to the drain. Both of these effects lead to the fact that it is necessary to raise the supply voltage to control the currents in the transistor, which negatively affects heat dissipation. So, by reducing the size of the transistor, we, first of all, reduce its gate and the layer of silicon dioxide (SiO2), which is a natural barrier between the gate and the channel. On the one hand, this improves the speed performance of the transistor (switching time), but on the other hand, it increases the leakage. That is, it turns out a kind of closed cycle. So the transition to 90 nm is another decrease in the thickness of the dioxide layer, and at the same time an increase in leaks. The fight against leakage is, again, an increase in control voltages, and, accordingly, a significant increase in heat generation. All this led to a delay in the introduction of a new technical process by competitors in the microprocessor market - Intel and AMD.

One alternative is to use SOI (silicon on insulator) technology, which AMD has recently introduced in its

64-bit processors. However, it cost her a lot of effort and overcoming a large number of incidental difficulties. But the technology itself provides a huge number of advantages with a relatively small number of disadvantages. The essence of the technology, in general, is quite logical - the transistor is separated from the silicon substrate by another thin layer of insulator. Pluses - weight. No uncontrolled movement of electrons under the transistor channel, affecting its electrical characteristics - again. After applying the unlocking current to the gate, the channel ionization time to the operating state, until the operating current flows through it, is reduced, that is, the second key parameter of the transistor performance improves, its turn-on / turn-off time is two. Or, at the same speed, you can simply lower the unlocking current - three. Or find some compromise between increasing the speed of work and reducing the voltage. While maintaining the same unlocking current, the increase in transistor performance can be up to 30%, if you leave the frequency the same, with an emphasis on energy saving, then there can be a big plus - up to 50%. Finally, the characteristics of the channel become more predictable, and the transistor itself becomes more resistant to sporadic errors, such as those caused by cosmic particles that enter the substrate of the channel and ionize it unexpectedly. Now, getting into the substrate located under the insulator layer, they do not affect the operation of the transistor in any way. The only disadvantage of SOI is that you have to reduce the depth of the emitter/collector region, which directly and directly affects its resistance increase as the thickness decreases.

And finally, the third reason that contributed to the slowdown in frequency growth is the low activity of competitors in the market. It can be said that everyone was busy with their own affairs. AMD was engaged in the widespread introduction of 64-bit processors, for Intel it was a period of improving the new technical process, debugging for an increased yield of suitable crystals.

The year that has begun should bring us a lot of news from the field of technology, because this year both companies should switch to 90 nm technology standards. But this does not at all mean a new rapid increase in processor frequencies, rather the opposite. At first, there will be a lull in the market: competitors will start producing CPUs based on new technical processes, but with old frequencies. As the production process is mastered, some increase in the frequency of chips will begin. Most likely, it will not be as noticeable as before. By the end of 2004, when 90nm die yields will rise significantly, Intel expects to hit the 4GHz top, or more. AMD processors will come with some traditional frequency lag, which, in general, does not affect performance as much as microarchitecture features.

So, the need to switch to new technical processes is obvious, but it is given to technologists every time with great difficulty. First processors

Pentium (1993) were produced according to the 0.8 micron process technology, then 0.6 micron. In 1995, the 0.35 micron process technology was used for the first time for the 6th generation processors. In 1997 it changed to 0.25 microns, and in 1999 to 0.18 microns. Modern processors are made using 0.13 and 0.09 micron technologies, the latter being introduced in 2004. As you can see, for these technical processes, Moore's law is observed, which states that every two years the frequency of crystals doubles with an increase in the number of transistors from them. The technological process is changing at the same pace. True, in the future the "frequency race" will outstrip this law. By 2006, Intel plans to master the 65-nm process technology, and 2009 - 32-nm. The principle of Moore's law is shown in Figure 1.

Figure 1 - The principle of Moore's law.

Here it is time to recall the structure of the transistor, namely, a thin layer of silicon dioxide, an insulator located between the gate and the channel, and performing a completely understandable function - a barrier to electrons that prevents leakage of the gate current. Obviously, the thicker this layer, the better it performs its insulating functions, but it is an integral part of the channel, and it is no less obvious that if we are going to reduce the channel length (transistor size), then we need to reduce its thickness, and, moreover, very at a fast pace. By the way, over the past few decades, the thickness of this layer has averaged about 1/45 of the entire length of the channel. But this process has its end - as Intel stated five years ago, if you continue to use SiO2, as it has been for the past 30 years, the minimum layer thickness will be 2.3. nm, otherwise the current leakage of the gate current will acquire simply unrealistic values.

Until recently, nothing has been done to reduce subchannel leakage, but now the situation is beginning to change, since the operating current,

along with shutter time, is one of the two main

parameters characterizing the speed of the transistor, and leakage in the off state directly affects it - in order to maintain the required efficiency of the transistor, it is necessary, accordingly, to raise the operating current, with all the ensuing conditions.

1.2 Main production steps

The manufacture of a microprocessor is a complex process that includes more than 300 stages. Microprocessors are formed on the surface of thin circular silicon plates - substrates, as a result of a certain sequence of various processing processes using chemicals, gases and ultraviolet radiation.

The substrates are typically 200 millimeters or 8 inches in diameter. However, Intel has already moved to 300 mm or 12-inch wafers. The new plates make it possible to obtain almost 4 times more crystals, and the yield is much higher. The wafers are made from silicon, which is refined, melted and grown into long cylindrical crystals. The crystals are then cut into thin plates and polished until their surfaces are mirror-smooth and free from defects. Further, thermal oxidation (formation of a SiO2 film), photolithography, impurity diffusion (phosphorus), epitaxy (layer buildup) are performed sequentially cyclically repeating.

In the process of manufacturing microcircuits, the thinnest layers of materials are applied to blank plates in the form of carefully calculated patterns. Up to several hundred microprocessors are placed on one plate, the manufacture of which requires more than 300 operations. The entire process of manufacturing processors can be divided into several stages: growing silicon dioxide and creating conductive regions, testing, manufacturing the package and delivery.

1.3 Growing silicon dioxide and creating conductive regions

The manufacturing process of a microprocessor begins with "growing" an insulating layer of silicon dioxide on the surface of a polished plate. This stage is carried out in an electric oven at a very high temperature. The thickness of the oxide layer depends on the temperature and the time the plate spends in the furnace.

This is followed by photolithography - a process during which a pattern is formed on the surface of the plate. First, a temporary layer of light-sensitive material, a photoresist, is applied to the plate, onto which an image of the transparent sections of the template, or photomask, is projected using ultraviolet radiation. Masks are made during processor design and are used to generate circuit patterns in each processor layer. Under the influence of radiation, the exposed areas of the photolayer become soluble, and they are removed with a solvent (hydrofluoric acid), revealing the silicon dioxide underlying them.

Exposed silica is removed by a process called "etching". The remaining photo layer is then removed, leaving a silicon dioxide pattern on the wafer. As a result of a number of additional operations of photolithography and etching, polycrystalline silicon, which has the properties of a conductor, is also applied to the wafer. During the next operation, called "doping", the exposed areas of the silicon wafer are bombarded with ions of various chemical elements, which form negative and positive charges in silicon, changing the electrical conductivity of these areas.

The imposition of new layers with subsequent etching of the circuit is carried out several times, while for interlayer connections in the layers "windows" are left, which are filled with metal, forming electrical connections between the layers. In its 0.13 micron process technology, Intel used copper conductors. In the 0.18 micron manufacturing process and previous generation processes, Intel used aluminum. Both copper and aluminum are excellent conductors of electricity. When using the 0.18-micron process technology, 6 layers were used; when introducing the 90 nm process technology in 2004, 7 layers of silicon were used.

Each layer of the processor has its own pattern, together all these layers form a three-dimensional electronic circuit. The application of layers is repeated 20-25 times over several weeks.

1.4 Testing

The silicon wafers must initially be sufficiently thick to withstand the stresses that the substrates are subjected to during the layering process. Therefore, before cutting the plate into individual microprocessors, its thickness is reduced by 33% using special processes and dirt is removed from the reverse side. Then, a layer of special material is applied to the reverse side of the "thinner" plate, which improves the subsequent fastening of the crystal to the case. In addition, this layer provides electrical contact between the rear surface of the integrated circuit and the package after assembly.

After that, the plates are tested to check the quality of all processing operations. To determine if the processors are working properly, their individual components are tested. If faults are detected, they are analyzed to understand at what stage of processing the failure occurred.

Electrical probes are then connected to each processor and power is applied. The processors are tested by the computer, which determines whether the characteristics of the manufactured processors meet the specified requirements.

1.5 Manufacture of the body

After testing, the wafers are sent to an assembly plant where they are cut into small rectangles, each containing an integrated circuit. A special precision saw is used to separate the plate. Non-working crystals are rejected.

Each crystal is then placed in an individual case. The case protects the crystal from external influences and provides its electrical connection with the board on which it will be subsequently installed. Tiny balls of solder located at certain points on the crystal are soldered to the electrical leads of the package. Now electrical signals can flow from the board to the chip and vice versa.

In future processors, Intel will use BBUL technology, which will allow the creation of fundamentally new cases with less heat dissipation and capacitance between CPU legs.

After the die is installed in the package, the processor is tested again to determine if it is operational. Faulty processors are rejected, and serviceable ones are subjected to stress tests: exposure to various temperature and humidity conditions, as well as electrostatic discharges. After each stress test, the processor is tested to determine its functional state. The processors are then sorted based on their behavior at various clock speeds and supply voltages.

Delivery. The processors that have passed the test go to the final control, the task of which is to confirm that the results of all previous tests were correct, and the parameters of the integrated circuit correspond to the established standards or even exceed them. All processors that pass the output control are labeled and packaged for delivery to customers

1.6 Production outlook

Founded by Robert Noyce and Gordon Moore in 1968, Intel (Integrated Electronics) has set itself the goal of using the achievements of semiconductor technology to create high-performance and complex-functional electronic devices on a silicon chip: large memory, processors, interface blocks. The company's first product was a Schottky bipolar transistor memory chip released in 1969. Intel announced the i4004, the world's first microprocessor designed for use in calculators, in November 1971. This 4-bit processor contained 2300 p-channel MOS transistors placed on a chip with an area of ​​​​3.8x2.8 mm, and worked at a clock frequency of 108 kHz, providing addressing of 4 KB of ROM and 512 bytes of RAM. This was the first development of Intel.

The Intel Pentium 4 processor is the most modern processor available today. The first Pentium 4 (codename Willamette) appeared in 2000. It was a fundamentally new processor with hyperpipeline (Hyper pipelining) - with a pipeline consisting of 20 stages, each of which is shortened. Binary compatible with previous generations of Intel architecture processors. According to Intel, processors based on this technology can achieve a frequency increase of about 40 percent over the P6 family with the same manufacturing process. This CPU is made using Intel NetBurst technology:

Hyper-pipelining technology: Extended pipeline length improves processor throughput.

SSE2 Streaming SIMD Extension Set: 144 new instructions to speed up a wide range of demanding applications

Faster Instruction Execution Engine: The arithmetic logic block runs at twice the clock speed of the processor, speeding up this critical performance area

128-bit floating-point unit: High-performance floating-point performance enhances 3D visualization, gaming applications, and scientific computing

128-bit integer SIMD engine: Accelerates video, speech, encryption, image and photo processing.

Level 1 Execution Trace Cache: Significantly improves the efficiency of the instruction cache, maximizing the performance of frequently accessed sections of code

Advanced Dynamic Execution Technology: Improved branch prediction improves performance for all 32-bit applications by optimizing instruction sequencing

Temperature control: Used to protect motherboards by detecting when the temperature exceeds the limit

Built-in Self-Testing Engine (BIST): A single mechanism for checking for firmware and large logic array errors, as well as testing instruction caches, data caches, translation buffers, and ROMs.

Test access port and boundary scan engine based on the IEEE 1149 standard. Allows you to test the Pentium 4 processor and its connection to the system through a standard interface.

A 100 (400) MHz system bus (Quad-pumped, QPB) was used, providing a bandwidth of 3.2 GB / s versus a 133 MHz bus with a bandwidth of 1.06 GB / s for the Pentium III. In fact, with an increase in the number of stages, the CPU frequency increases, but the operations are processed longer. Thus, Willamette became "stupid" with increasing frequency; operations began to pass through a larger number of steps, and the processing time for one instruction increased. So, the processor turned out to be weak, even with an excellent FSB, its performance did not differ much from Tualatin, and the price, including for the chipset and RDRAM memory, did not please, and it was not in particular demand.

Specifications: production technology: 0.18 microns; clock frequency: 1.3-2 GHz; first level cache: 8 +12 KB; second-level cache using Advanced Transfer Cache technology 256 KB (full-speed); CPU

32-bit; data bus 64-bit (400 MHz); connector Socket-423 and Socket-478; core voltage - 1.75 V.

To turn things around in the mainstream and performance segments, Tualatin was left under Celeron, while Intel introduced a new Northwood core made using 0.13 micron technology. There are now 3 modifications: Northwood-A with 100 (400), Northwood-B 133 (533) MHz and Northwood-C 200 (800) MHz system bus. The only differences in the architecture are the 0.13-micron manufacturing technology and the L2 cache increased to 512 KB, which has put Intel in the lead at the moment. The main competitor - the Athlon XP processor based on the Barton core - has approximately the same parameters, except for a smaller number of stages in the pipeline, and, accordingly, a lower frequency of the crystal and the system bus. Both processors have about the same performance.

In the meantime, Intel has moved the value segment to the P4 Willamette-128 core as well. This is a 32-bit superscalar CISC core of IA-32 architecture, which is produced according to the technological standards of 0.18 microns, has an 8 KB first-level cache for data and a trace cache for 12 thousand microops, a long pipeline for 20 stages; the external bus has a capacity of 64 bits, a frequency of 100 (400) MHz, a quadruple data stream (equivalent to a frequency of 400 MHz). The L2 cache built into the core of the original Willamette was 256 KB, but the Celeron's was cut down to 128 KB. Available with clock frequencies of 1.7-2.4 GHz. The performance is lower than AMD Duron core Morgan and Applebred.

In 2003, Intel announced a new feature of the Northwood core - Hyper-Threading technology allows you to artificially parallelize program code into several threads ("threads") and simultaneously execute them while emulating the presence of a second processor on a single chip. In this case, all unused CPU blocks are used, which allows the most efficient use of CPU blocks.

The last desktop Pentium 4 based on the Northwood core was a model with a clock speed of 3.40 GHz and 512 KB of L2.2 cache. On February 2004, Intel announced a new Prescott core for the Pentium 4, made using 0.09 micron technology with a 1 MB L2 cache. Based on the new core, processors with frequencies from 2.80 GHz to 3.40 GHz will be released for the time being. Models with 800 MHz bus at 2.80, 3, 3.20 and 3.40 GHz are labeled E to distinguish them from models with the same frequency and bus on the Northwood core. In the third quarter of 2004, the Pentium 4 will be released with a clock speed of 3.80 GHz, and by the end of the year it is quite possible to expect the conquest of the symbolic milestone of 4 GHz.

The main "features" of the new core are its complete redesign, a pipeline extended to 31 stages, a new manufacturing technology using strained silicon technology and a CDO dielectric in interconnects, as well as 13 new instructions (SSE3), improved Hyper-Threading technology, transition prediction and preliminary cache fetching; and power management.

In addition, integer multiplication operations have been accelerated, additional write buffers have been introduced. In addition, the new product should have support for 64-bit instructions, which are not compatible with 64-bit AMD instructions and are blocked, at least for now. The new processor includes LaGrande hardware data encryption technology, but software support will appear later. The new die has an area of ​​112 mm2 and contains 125 million transistors. Because of this, the thermal regime of the new processor has also changed - the FMB 1.5 specification. The thermal package has now expanded its ranges: the older model will have a heat dissipation of 103 watts. This causes compatibility issues with most motherboards available. So far, all processors have Socket 478, but due to the increase in power consumption, it will soon be replaced by Socket 775 with 775 pins, respectively. Prices for this line range from $163 to $417, but will soon catch up with Northwood to stimulate demand.

In parallel, Intel is developing the EPIC technology used in its 64-bit server processors. This technology, which is used to manufacture modern Intel Itanium 2 processors, implies full parallelism of instructions sent by the compiler to the processor. This architecture is called IA-64.

However, the traditional IA-32 architecture has not yet fully exhausted itself, so its existence is expected until 2006. It's too early to talk about the year 2005, because the convergence is gaining momentum, and Moore's law is still valid. Although, in principle, it is already obvious that the increase in frequency and the increase in cache no longer bring the proper increase in performance, so the companies decided to rely on technology. The increase in frequency while maintaining the growth of heat release is no longer possible due to a sharp increase in the leakage currents of transistors. Since the microarchitecture cannot be improved indefinitely, and there is no point in that, it is obvious that the future lies in the integration of various technologies and capabilities into chips. So Intel in the server sector relies on multi-core, and in the desktop segment - on multi-threading. AMD, however, not wanting to make huge investments in such research, immediately "goes like a horse": everywhere it promotes the production technology of SOI (Silicon-on-Insulator) and relies on expanding the microarchitecture to 64 bits, as well as on the HyperTransport bus.

2. Features of the production of microprocessors

It is known that existing CMOS transistors have many limitations and will not allow raising processor frequencies in the near future as painlessly. At the end of 2003, at the Tokyo conference, Intel made a very important announcement about the development of new materials for semiconductor transistors of the future. First of all, we are talking about a new transistor gate dielectric with a high dielectric constant (the so-called "high-k" material), which will be used to replace the silicon dioxide (SiO2) used today, as well as new metal alloys compatible with the new gate dielectric . The solution proposed by the researchers reduces the leakage current by 100 times, which makes it possible to come close to the introduction of a manufacturing process with a design norm of 45 nanometers. It is considered by experts as a small revolution in the world of microelectronic technologies.

To understand what we are talking about, let's first look at a conventional MOSFET, on the basis of which the most complex CPUs are made. The MOSFET is shown in Figure 2.

Figure 2 - MOSFET.

In it, a conductive polysilicon gate is separated from the transistor channel by the thinnest (only 1.2 nm or 5 atoms thick) layer of silicon dioxide (a material used for decades as a gate dielectric).

Such a small dielectric thickness is necessary to obtain not only small dimensions of the transistor as a whole, but also for its highest performance (charged particles move faster through the gate, as a result of which such a VT can switch up to 10 billion times per second)

Simplified - the closer the gate to the transistor channel (that is, the thinner the dielectric), the "greater impact" in terms of speed it will have on the electrons and holes in the transistor channel. The appearance of the insulating layer of the gate is shown in Figure 3.

Figure 3 - External view of the insulating layer of the gate.

Therefore, the importance of the discovery of Intel scientists cannot be underestimated. After five years of research in laboratories, the corporations have developed a special material to replace traditional silicon dioxide in the conventional chip manufacturing route. The requirements for such a material are very serious: high chemical and mechanical (at the atomic level) compatibility with silicon, ease of production in a single cycle of the traditional silicon process technology, but most importantly - low leakage and high dielectric constant.

If we are struggling with leaks, then the thickness of the dielectric must be increased to at least 2-3 nm (see the figure above). In order to maintain the previous transconductance of the transistor (dependence of current on voltage), it is necessary to proportionally increase the dielectric constant of the dielectric material. An insulator with a high dielectric constant is shown in Figure 4.

Picture 4 - An insulator with a high dielectric constant.

If the permeability of bulk silicon dioxide is equal to 4 (or slightly less in ultrathin layers), then a reasonable value of the dielectric constant of the new "Intel" dielectric can be considered a value in the region of 10-12. Despite the fact that there are many materials with such a permittivity (capacitor ceramics or a single crystal of silicon), the factors of technological compatibility of materials are no less important here. Therefore, for the new high-k-material, a high-precision deposition process was developed, shown in Figure 5, during which one molecular layer of this material is formed in one cycle.

Figure 5 - Scheme of the high-precision process of applying the High-K layer.

Based on this picture, it can be assumed that the new material is also an oxide. Moreover, monoxide, which means the use of materials mainly of the second group, for example, magnesium, zinc or even copper.

But the matter was not limited to the dielectric. It was also necessary to change the material of the shutter itself - the usual polycrystalline silicon. The fact is that the replacement of silicon dioxide with a high-k dielectric leads to problems of interaction with polycrystalline silicon (the band gap of a transistor determines the minimum possible voltage for it). These problems can be eliminated by using special gate metals for both types of transistors (n-MOS and p-MOS) in combination with a special manufacturing process. This combination of materials achieves record-breaking transistor performance and uniquely low leakage currents, 100 times lower than current materials. In this case, there is no longer a temptation to use the much more expensive SOI (silicon on insulator) technology to combat leaks, as some major microprocessor manufacturers do. Characteristics of High-K coated transistors are shown in Figure 6.

Figure 6 - Characteristics of High-K coated transistors.

We also note another technological innovation from Intel - strained silicon technology, which is used for the first time in 90-nanometer processors Prescott and Dothan. Finally, Intel has explained in detail exactly how the layers of stressed silicon are formed in its CMOS structures. A CMOS cell consists of two transistors, an nMOS and a pMOS. A CMOS cell of two transistors is shown in Figure 7.

Figure 7 - CMOS cell of two transistors.

In the first (n-MOS), the transistor channel (n-channel) conducts current with the help of electrons (negatively charged particles), and in the second (p-MOS) - with the help of holes (conditionally positively charged particles). Accordingly, the mechanisms of strained silicon formation in these two cases are different. For the n-MOS transistor, an external coating with a layer of silicon nitride (Si3N4) is used, which, due to mechanical stresses, slightly (by a fraction of a percent) stretches (in the direction of current flow) the silicon crystal lattice under the gate, as a result of which the channel operating current increases by 10% (relatively speaking, it becomes more spacious for electrons to move in the direction of the channel). In p-MOS transistors, the opposite is true: the substrate material (more precisely, only the drain and source regions) uses a silicon-germanium compound (SiGe), which slightly compresses the silicon crystal lattice under the gate in the direction of the channel. Therefore, it becomes "easier" for holes to "move" through acceptor impurity atoms, and the operating current of the channel increases by 25%. The combination of both technologies gives a 20-30% current gain. Thus, the use of "stressed silicon" technology in both types of devices (n-MOS and p-MOS) leads to a significant increase in transistor performance with an increase in the cost of their production by only ~2% and makes it possible to create more miniature transistors of the next generations. Intel plans to use strained silicon for all future manufacturing processes up to 22nm. A 6-transistor memory cell is shown in Figure 8.

Figure 8 - 6-transistor memory cell.

A low dielectric material is used as the dielectric for copper junctions (see figure) in all Intel processes starting at 0.13 micron. It reduces the capacitance that occurs between the copper connections on the chip, which increases the transfer rate of internal signals and reduces power consumption. Intel is the first and so far the only company to use this low-k material for interconnect insulation. The connections in the chip created using the 90-nm process technology are shown in Figure 9.

Figure 9 - Connections in a chip created using a 90-nm process technology.

Yes, it must be admitted that the success of the Intel Labs in the development of innovative semiconductor technologies is impressive. Typically, Intel manages to stay one step ahead of other competitors such as IBM, Motorola, and Texas Instruments. On the other hand, this is not surprising - after all, Intel's development costs this year alone amounted to about 4.3 billion US dollars! And now the statements about the unprofitability and complexity of SOI technology are becoming clear, which Intel has already endured in its own skin, and AMD has just taken up them. Well, the huge scientific potential allows the company not only to look ahead into the future of microprocessor technologies for several years ahead, but also to predict changes in the world of technology and be an active participant in these changes. This is the price a company pays for making history with its own hands, and not being its bystander. This is the true face of a technology leader.

3. Technological stages of microprocessor production

3.1 How chips are made

The production of chips consists in the imposition of thin layers with a complex "pattern" on silicon substrates. First, an insulating layer is created that acts as an electrical shutter. A photoresist material is then applied on top, and unwanted areas are removed using masks and high-intensity irradiation. When the irradiated areas are removed, areas of silicon dioxide will open underneath, which is removed by etching. After that, the photoresistive material is also removed, and we get a certain structure on the silicon surface. Then additional photolithography processes are carried out, with different materials, until the desired three-dimensional structure is obtained. Each layer can be doped with a certain substance or ions, changing the electrical properties. Windows are created in each layer in order to then bring metal connections.

As for the production of substrates, they must be cut from a single single-crystal-cylinder into thin "pancakes" in order to be easily cut into separate processor crystals later. Sophisticated testing is carried out at every step of production to assess the quality. Electrical probes are used to test each chip on the substrate. Finally, the substrate is cut into individual cores, non-working cores are immediately eliminated. Depending on the characteristics, the core becomes one or another processor and is enclosed in a package that facilitates the installation of the processor on the motherboard. All functional blocks go through intensive stress tests.

1.2 It all starts with substrates

The first step in processor manufacturing is done in a clean room. By the way, it is important to note that such a technological production is an accumulation of huge capital per square meter. The construction of a modern plant with all the equipment easily "flies away" 2-3 billion dollars, and it takes several months to test runs of new technologies. Only then can the plant mass-produce processors.

In general, the chip manufacturing process consists of several substrate processing steps. This includes the creation of the substrates themselves, which will eventually be cut into individual crystals.

1.3 Substrate production

It all starts with growing a single crystal, for which the seed crystal is embedded in a bath of molten silicon, which is located just above the melting point of polycrystalline silicon. It is important that the crystals grow slowly (about a day) to ensure that the atoms are arranged correctly. Polycrystalline or amorphous silicon is made up of many assorted crystals that will result in unwanted surface structures with poor electrical properties.

Once the silicon is melted, it can be doped with other substances that change its electrical properties. The whole process takes place in a sealed room with a special air composition so that the silicon does not oxidize.

The single crystal is cut into "pancakes" using a circular diamond saw, which is very accurate and does not create large irregularities on the surface of the substrates. Of course, in this case, the surface of the substrates is still not perfectly flat, so additional operations are needed. The appearance of the single crystal is shown in Figure 10.

Figure 10 - Appearance of a single crystal.

First, using rotating steel plates and an abrasive material (such as aluminum oxide), a thick layer is removed from the substrates (a process called lapping). As a result, irregularities ranging in size from 0.05 mm to approximately 0.002 mm (2,000 nm) are eliminated. The edges of each substrate should then be rounded off, as sharp edges can cause the layers to peel off. Next, the etching process is used, when using various chemicals (hydrofluoric acid, acetic acid, nitric acid) the surface is smoothed by about 50 microns. There is no physical deterioration of the surface as the whole process is completely chemical. It allows you to remove the remaining errors in the crystal structure, as a result of which the surface will be close to ideal.

The last step is polishing, which smoothes the surface down to roughness, maximum 3 nm. Polishing is done with a mixture of sodium hydroxide and granular silica.

Today, microprocessor wafers are 200 or 300 mm in diameter, allowing chip makers to get many processors from each wafer. The next step will be 450 mm substrates, but before 2013 they should not be expected. In general, the larger the wafer diameter, the more chips of the same size can be produced. A 300 mm wafer, for example, yields more than twice as many processors as a 200 mm wafer.

1.4 Doping, diffusion

We have already mentioned doping, which is carried out during the growth of a single crystal. But doping is carried out both with the finished substrate and during

the time of photolithography processes later. This allows you to change the electrical properties of certain regions and layers, and not the entire structure of the crystal.

The addition of a dopant may occur via diffusion. Dopant atoms fill the free space inside the crystal lattice, between silicon structures. In some cases, the existing structure can also be doped. Diffusion is carried out with the help of gases (nitrogen and argon) or with the help of solids or other sources of dopant.

Another approach to doping is ion implantation, which is very useful in changing the properties of a substrate that has been doped, since ion implantation is carried out at ordinary temperature. Therefore, existing impurities do not diffuse. A mask can be applied to the substrate, which allows you to process only certain areas. Of course, one can talk about ion implantation for a long time and discuss the penetration depth, additive activation at high temperature, channel effects, penetration into oxide levels, etc., but this is beyond the scope of our article. The procedure can be repeated several times during production.

1.5 Create a mask

To create sections of an integrated circuit, the process of photolithography is used. Since in this case it is not necessary to irradiate the entire surface of the substrate, it is important to use the so-called masks, which transmit high-intensity radiation only to certain areas. Masks can be compared to a black and white negative. Integrated circuits have many layers (20 or more), and each of them requires its own mask.

A thin chrome film structure is applied to the surface of a quartz glass plate to create a template. At the same time, expensive tools using an electron beam or a laser write the necessary data of an integrated circuit, as a result of which we get a pattern of chromium on the surface of a quartz substrate. It is important to understand that each modification of the integrated circuit leads to the need to produce new masks, so the whole process of making changes is very costly. The appearance of the EUV mask is shown in Figure 11.

Figure 11 - Appearance of the EUV mask.

1.6 Photolithography

Using photolithography, a structure is formed on a silicon substrate. The process is repeated several times until many layers (more than 20) are created. Layers can consist of different materials, moreover, you also need to think through the connections with microscopic wires. All layers can be alloyed.

Before the photolithography process begins, the substrate is cleaned and heated to remove sticky particles and water. The substrate is then coated with silicon dioxide using a special device. Next, a bonding agent is applied to the substrate, which ensures that the photoresist material that will be applied in the next step remains on the substrate. The photoresist material is applied to the middle of the substrate, which then begins to rotate at high speed so that the layer is evenly distributed over the entire surface of the substrate. The substrate is then heated again. The principle of operation of photolithography is shown in Figure 12.

Figure 12 - The principle of operation of photolithography.

The cover is then irradiated through the mask with a quantum laser, hard ultraviolet radiation, x-rays, electron or ion beams - all of these sources of light or energy can be used. Electron beams are mainly used for masks, X-rays and ion beams for research purposes, and industrial production today is dominated by hard UV radiation and gas lasers. Types of cover exposure sources are shown in Figure 13.

Figure 13 - Types of cover exposure sources.

Hard UV radiation at a wavelength of 13.5 nm irradiates the photoresist material as it passes through the mask.

Projection time and focus are very important to obtain the desired result. Poor focusing will result in extra particles of photoresist material remaining, as some holes in the mask will not be irradiated properly. The same will happen if the projection time is too short. Then the photoresist structure will be too wide, the areas under the holes will be underexposed. On the other hand, excessive projection time creates too large areas under the holes and too narrow a photoresist structure. As a rule, it is very time-consuming and difficult to adjust and optimize the process. Unsuccessful adjustment will lead to serious deviations in the connecting conductors.

A special stepping projection unit moves the substrate to the desired position. Then a line or one section can be projected, most often corresponding to one processor chip. Additional micro settings may make additional changes. They can debug existing technology and optimize the process. Micro-installations usually work on areas less than 1 sq. mm, while conventional installations cover larger areas.

Etching and cleaning of the substrate are shown in Figure 14.

Figure 14 - Etching and cleaning of the substrate.

The substrate then proceeds to a new stage where the weakened photoresist material is removed, allowing access to the silicon dioxide. There are wet and dry etch processes that treat areas of silicon dioxide. Wet processes use chemical compounds, while dry processes use gas. A separate process is to remove the remnants of the photoresist material. Manufacturers often combine wet and dry removal so that the photoresist material is completely removed. This is important because the photoresist material is organic and, if left unremoved, can cause defects in the substrate.

After etching and cleaning, you can proceed to the inspection of the substrate, which usually happens at each important stage, or transfer the substrate to a new cycle of photolithography.

The substrate test is shown in Figure 15.

Figure 15 - Substrate test is shown in the figure.

Finished substrates are tested on the so-called probe control units. They work with the entire substrate. Probe contacts are superimposed on the contacts of each crystal, allowing electrical tests to be carried out. The software tests all the functions of each core.

Cutting the substrate is shown in Figure 16.

Figure 16 - Substrate cutting is shown.

By cutting from the substrate, individual nuclei can be obtained. At the moment, the probe control installations have already identified which crystals contain errors, so after cutting they can be separated from the good ones. Previously, damaged crystals were physically marked, now this is not necessary, all information is stored in a single database.

The functional core then needs to be bonded to the processor package using adhesive material.

The wire connection of the substrate is shown in Figure 17.

Figure 17. - Wired connection of the substrate.

Then you need to make wire connections connecting the contacts or legs of the package and the crystal itself. Gold, aluminum or copper connections can be used.

Processor packaging is shown in Figure 18.

Figure 17 - Processor packaging.

Most modern processors use plastic packaging with a heat spreader. Typically, the core is encased in ceramic or plastic packaging to prevent damage. Modern processors are equipped with a so-called heat spreader, which provides additional protection for the crystal, as well as a large contact surface with the cooler.

The last stage involves testing the processor, which occurs at elevated temperatures, in accordance with the specifications of the processor. The processor is automatically installed in the test socket, after which all the necessary functions are analyzed.

Conclusion

The production of microprocessors consists of two important stages. The first is in the production of the substrate, which AMD and Intel do in their factories. This includes imparting conductive properties to the substrate. The second stage is the test of substrates, assembly and packaging of the processor. The last operation is usually performed in less expensive countries. If you look at Intel processors, you will find that the packaging was made in Costa Rica, Malaysia, the Philippines, etc.

AMD and Intel are now trying to produce products for the maximum number of market segments, moreover, based on the minimum possible assortment of crystals. A perfect example is the Intel Core 2 Duo line of processors. There are three codenamed processors for different markets: Merom for mobile applications, Conroe for the desktop version, Woodcrest for the server version. All three processors are built on the same technological basis, which allows the manufacturer to make decisions at the last stages of production. Features can be enabled or disabled, and the current clock rate gives Intel an excellent chip yield rate. If the demand for mobile processors increases in the market, Intel can focus on the release of Socket 479 models. If the demand for desktop models increases, then the company will test, validate and package chips for Socket 775, while server processors are packaged for Socket 771. So even four-core processors are being created: two dual-core crystals are installed in one package, so we get four cores.

Bibliography

1. Muller S. Modernization and repair of PC, M.: 2003.

2. Asmakov S. Technologies for creating an element base, Computer-Press, No. 1, p. 29, 2007.

3. Asmakov S. New technologies, Computer-Press, No. 1, p. 36, 2007.

4. Pakhomov S. Modern processors for PC, Computer-Press, No. 12, p. 22, 2006.

5. Pakhomov S. Solutions based on Intel Itanium 2 processors, No. 9, p. 12, 2006.

Recently, in the Moscow Polytechnic Museum, the computer equipment stand has been seriously updated - Intel placed its stand there, which was called " From sand to processor"From now on, this stand will become an integral part of school excursions, but even adults I advise you not to postpone visiting the institution for more than five years - by 2016, Intel plans to seriously "upgrade" the museum so that it can enter the top ten science museums in the world!

The cycle of lectures of the same name in three parts was timed to coincide with this event. Two lectures have already passed - you can find their contents under the cut. Well, if you are interested in all this, then you will still have time to attend the third lecture, information about which is at the end of the post.

I am not ashamed to admit that most of this text is indeed a summary of the first lecture that Nikolay Suetin, director of external projects in the field of research and development of Intel in Russia. For the most part, it was about modern semiconductor technologies and the problems that they face.

I propose to start reading interesting things, and we will start with the very basics.

CPU

Technically, a modern microprocessor is made in the form of a single ultra-large integrated circuit, consisting of several billion elements - this is one of the most complex structures created by man. The key elements of any microprocessor are discrete switches - transistors. By blocking and passing electric current (on-off), they enable the computer's logic circuits to work in two states, that is, in a binary system. Transistors are measured in nanometers. One nanometer (nm) is one billionth (10−9) of a meter.
The main part of the work when creating processors is not done by people at all, but by robotic mechanisms - it is they who drag silicon wafers back and forth. The production cycle of each plate can be up to 2-3 months.

In more detail (and visually) about the production technology of processors, I will tell you, but for now, quite briefly.

The plates are indeed made of sand - in terms of prevalence in the earth's crust, silicon ranks second after oxygen. Through chemical reactions, silicon oxide (SiO 2) is thoroughly purified, making clean from “dirty”. For microelectronics, single-crystal silicon is needed - it is obtained from a melt. It all starts with a small crystal (which is lowered into the melt) - later it turns into a special single-crystal “boule” as tall as a person. Next, the main defects are removed and the boule is cut into disks with special threads (with diamond powder) - each disk is carefully processed to an absolutely even and smooth (at the atomic level) surface. The thickness of each plate is about 1mm - solely so that it does not break or bend, that is, so that it can be comfortably worked with.

The diameter of each plate is exactly 300mm - a little later hundreds or even thousands of processors will "grow" on this area. By the way, Intel, Samsung, Toshiba and TSMC have already announced that they are developing equipment capable of working with 450mm wafers (more processors will fit in a larger area, which means that the price of each will be lower) - the transition to them is planned for 2012.

Here is a cross-sectional image of the processor:

There is a protective metal cover on top, which, in addition to the protective function, also acts as a heat spreader - we generously smear it with thermal paste when we install the cooler. Under the heat spreader is the very piece of silicon that performs all user tasks. Even lower is a special substrate, which is needed for wiring contacts (and increasing the area of ​​\u200b\u200bthe "legs") so that the processor can be installed in the motherboard socket.

The chip itself consists of silicon, on which there are up to 9 metallization layers (made of copper) - exactly so many levels are needed so that, according to a certain law, it is possible to connect transistors located on the silicon surface (since it is simply impossible to do all this at the same level). In fact, these layers act as connecting wires, only on a much smaller scale; so that the "wires" do not short each other, they are separated by a layer of oxide (with a low dielectric constant).

As I wrote above, the elementary cell of the processor is a field effect transistor. The first semiconductor products were from germanium and the first transistors were made from it. But as soon as field-effect transistors began to be made (under the gate of which there is a special insulating layer - a thin dielectric film that controls the “on” and “off” of the transistor), germanium immediately “died out”, giving way to silicon. For the past 40 years, silicon dioxide (SiO 2 ) has been used as the main gate dielectric material, due to its manufacturability and the ability to systematically improve the characteristics of transistors as they become smaller.

The scaling rule is simple - by reducing the size of the transistor, the thickness of the dielectric should decrease proportionally. For example, in chips with a manufacturing process of 65 nm, the thickness of the SiO 2 gate dielectric layer was about 1.2 nm, which is equivalent to five atomic layers. In fact, this is the physical limit for this material, since as a result of further reduction of the transistor itself (and hence the reduction of the silicon dioxide layer), the leakage current through the gate dielectric increases significantly, which leads to significant current losses and excessive heat generation. In this case, the silicon dioxide layer ceases to be an obstacle to quantum tunneling of electrons, which makes it impossible to control the state of the transistor. Accordingly, even with the ideal manufacture of all transistors (the number of which in a modern processor reaches several billion), the incorrect operation of at least one of them means the incorrect operation of the entire processor logic, which can easily lead to disaster - this is if we consider that microprocessors control the operation of almost all digital devices (from modern cell phones to car fuel systems).

The process of miniaturization of transistors did not go against the laws of physics, but, as we can see, computer progress did not stop either. This means that the problem with the dielectric was somehow solved. And after all, they really decided - when switching to 45nm, Intel began to use a new material, the so-called high-k dielectric, which replaced the unpromisingly thin layer of silicon dioxide. The layer based on rare-earth hafnium oxide with a high (20 versus 4 for SiO 2) dielectric constant k (high-k) became thicker, but this made it possible to reduce the leakage current by more than ten times, while maintaining the ability to correctly and stably control transistor operation. The new dielectric turned out to be poorly compatible with a polysilicon gate, but this did not become an obstacle - to increase the speed, the gate in the new transistors was made of metal.

Thus, Intel became the first company in the world to mass-produce microprocessors using hafnium. Moreover, the palm still belongs to the corporation - so far no one can reproduce this technology, because. A dielectric film is created by atomic sputtering, with the material deposited in successive layers just one atom thick.
Interestingly, after reading these paragraphs, did you have an idea about how billions of transistors are designed, made and fit in such a small area? And how does it all work in the end and, at the same time, costs quite reasonable money? I became very thoughtful, although I used to consider all this obvious and I even had the conscience to think “ Hey, why so expensive? For one processor only!»:)

In 1965, one of the founders of Intel Corporation, Gordon Moore, recorded an empirical observation that later became the famous law of his name. Having presented the growth in the performance of memory chips in the form of a graph, he discovered an interesting pattern: new models of microcircuits were developed after equal periods of time - approximately 18-24 months - after the appearance of their predecessors, and the capacity of the microcircuits approximately doubled each time.

Later, Gordon Moore predicted a pattern, suggesting that the number of transistors in microprocessors would double every two years - in fact, constantly creating innovative technologies, Intel has been ensuring the implementation of Moore's law for more than 40 years.

The number of transistors continues to grow, although the dimensions of the "output" processor remain relatively unchanged. Again, there is no secret - it becomes clear if you look at the following dependence.

As you can see, every two years the topological dimensions decrease by 0.7 times. As a result of reducing the size of transistors, their switching speed is higher, the price is lower and the power consumption is lower.

At the moment, Intel releases processors using 32nm technology. Key technical differences from 45nm technology:
- 9 levels of metallization are used
- a new generation high-k dielectric is used (also hafnium oxide, but with special additives - the resulting layer is equivalent to 0.9nm silicon oxide)

The creation of a new technological process for creating a metal gate led to a 22% increase in the performance of all transistors (compared to 45nm), as well as the highest element density, which required the highest current density.

Production

Intel manufactures processors in three countries - the United States, Israel and Ireland. At the moment, the company has 4 factories for mass production of processors using 32nm technology. This is: D1D and D1C in Oregon, Fab 32 in Arizona and Fab 11X in New Mexico. And in the arrangement of these plants and in their work there are many interesting things, but I will talk about this next time.

The cost of such a plant is about $5 billion, and if you make several plants at once, then the amount of investment can be safely multiplied. If we take into account that technology is changed every two years, then it turns out that the plant has exactly 4 years to “recapture” the $5 billion invested in it and make a profit. From which the obvious conclusion suggests itself - the economy very much dictates the development of technological progress ... but, despite all these huge numbers, the cost of manufacturing one transistor continues to fall - now it is less than one billionth of a dollar.

Do not think that with the transition of several factories to 32nm, everything will suddenly be produced according to this technical process - the same chipsets and other peripheral circuits simply do not need this - in most cases they use 45nm. The milestone of 22nm is planned to be fully reached next year, and by 2013 there will most likely be 16nm. At least this year, a test plate (at 22nm) has already been made, on which the performance of all the elements necessary for the processor to work was demonstrated.

*upd from* The need to reduce the thickness of the gate dielectric is dictated by the simple formula of a flat capacitor:

The gate area of ​​the transistor decreases, and for the transistor to work, the capacitance of the gate dielectric must be maintained.
Therefore, it was necessary to reduce its thickness, and when it became impossible, a material with a higher dielectric constant was found.

When will the era of silicon end? The exact date is still unknown, but it is definitely not far off. In 22nm technology, it will definitely “fight”, most likely it will remain in 16nm ... but then the most interesting will begin. The periodic table, in principle, is quite large and there is plenty to choose from) But most likely, everything will rest not only in chemistry. It will be possible to achieve an increase in the efficiency of the processor either by reducing the topological dimensions (they are doing this now), or by using other compounds with higher carrier mobility - perhaps gallium arsenide, perhaps the "notorious" and promising graphene (by the way, it has mobility hundreds of times higher than silicon). But there are problems here too. Now the technologies are designed for processing plates with a diameter of 300 mm - the amount of gallium arsenide needed for such a plate is simply not in nature, and graphene (Word insistently suggests writing "decanter") of this size is still extremely difficult to manufacture - they learned how to do it, but there are many defects, problems reproduction, doping, etc.

Most likely, the next step will be the deposition of single-crystal gallium arsenide on silicon, and then graphene. And, perhaps, the development of microelectronics will go not only along the path of improving technologies, but also along the path of developing a fundamentally new logic - after all, this cannot be ruled out either. Shall we bet, gentlemen? ;)

In general, now there is a struggle for technology and high mobility. But one thing is clear - there is no reason to stop progress.

tick tock

The manufacturing process of processors consists of two large "parts". For the first, you need to have the manufacturing technology itself, and for the second, you need an understanding of WHAT to manufacture and how - the architecture (how the transistors are connected). If both a new architecture and a new technology are made at the same time, then in case of failure it will be difficult to find the “guilty” - some will say that the “architects” are to blame, others that the technologists. In general, to follow such a strategy is very short-sighted.

In Intel, the introduction of a new technology and architecture is spaced out in time - a technology is introduced in one year (and an already proven architecture is produced according to a new technology - if something goes “wrong”, then the technologists will be to blame); and when the new technology is worked out, the architects will make a new architecture for it, and if something does not work on the proven technology, then the architects will be to blame. This strategy was called “tick-tock”.
More clearly:

With the current pace of technology development, a fantastic amount of investment in research and development is required - annually Intel invests $ 4-5 billion in this business. Some of the work takes place within the company, but a lot of work takes place outside of it. Just keep an entire laboratory in the company like Bell Labs(forge of Nobel laureates) in our time is almost impossible.
As a rule, the first ideas are laid in universities - in order for universities to know what exactly it makes sense to work on (what technologies are in demand and what will be relevant), all “semiconductor companies” were united into a consortium. After that, they provide a kind of roadmap - it talks about all the problems that will face the semiconductor industry in the next 3-5-7 years. In theory, any company has the right to literally go to the university and "use" this or that innovative development, but the rights to them, as a rule, remain with the developer university - this approach is called "open innovations". Intel is no exception and periodically listens to the ideas of students - after protection, selection at the engineering level and testing in real conditions, the idea has every chance of becoming a new technology.

Here is a list of research centers around the world that Intel works with (excluding universities):

Increasing productivity leads to more expensive factories, and this in turn leads to natural selection. So, for example, to pay for itself in 4 years, each Intel factory must produce at least 100 working wafers per hour. There are thousands of chips on each wafer... and if you make certain calculations, it will become clear that if Intel didn't have 80% of the world processor market, the company simply would not be able to recoup the costs. The conclusion is that in our time it is quite expensive to have both your own "design" and your own production - at least you need to have a huge market. The result of natural selection can be seen below - as you can see, with their "design" and production, fewer and fewer companies keep pace with technological progress. Everyone else had to switch to fabless mode - for example, neither Apple, nor NVIDIA, nor even AMD have their own factories and they have to use the services of other companies.

In addition to Intel, only two companies around the world are potentially ready for 22nm technology - Samsung and TSMC, which invested more than $ 1 billion in their factories last year. Moreover, TSMC does not have its own design division (only foundry) - in fact, it is just a high-tech forge that takes orders from other companies and often does not even know what it forges.

As you can see, natural selection took place quite quickly - in just 3 years. From this, two conclusions can be drawn. The first is that it is unlikely to become an industry leader without your own factory; the second - in fact, you can succeed without your own factory. By and large, a good computer, brains and the ability to "draw" will suffice - the threshold for entering the market has greatly decreased and it is for this reason that a lot of "startups" have appeared. Someone comes up with a certain scheme for which there is or is artificially created a certain market - novice manufacturers rise ... PROFIT! But the threshold for the foundry market has risen a lot and will only grow further ...

What else has changed in recent years? If you remember, then until 2004 the statement “the higher the frequency of the processor, the better” was quite fair. Starting from 2004-2005, the frequency of processors almost stopped growing, which is connected with reaching some kind of physical limitations. Now you can increase productivity due to multi-core - performing tasks in parallel. But making many cores on a single chip is not a big problem - it is much more difficult to get them to work correctly under load. As a result, from that moment on, the role of software has increased dramatically and the importance of the “programmer” profession will only gain momentum in the near future.

In general, summing up the above:
- Moore's Law still applies
- The cost of developing new technologies and materials, as well as the costs of maintaining factories, are rising
- Productivity is also growing. A jump is expected when moving to 450mm plates

As a result:
- Separation of companies into "fabless" and "foundry"
- Outsource core R&D
- Differentiation through software development

The end

Did you enjoy reading? Hope. At the very least, it was interesting for me to write all this, and it was even more interesting to listen to it ... although at first I also thought, “what will they tell at this lecture.”

Last week, the second lecture was held at the Moscow Polytechnic Museum, which